Private Draft

The 29 personas behind AI

We’ve organized every stage and persona in the AI supply chain, informed by real recruiting at frontier companies. Click any row to see matching profiles from our talent graph.

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AI Hardware

Designs AI compute silicon

AI Hardware

Summary

Known as: ASIC Engineer, Chip Architect, Hardware Engineer, Mechanical Design Engineer, Process Engineer, Reliability Engineer, Test Engineer (Silicon), Packaging Engineer

Designs and builds compute hardware for AI workloads: custom accelerators, chip architectures, silicon, and the manufacturing pipeline from tape-out through volume production. For robotics, includes mechanical design, actuator systems, and electromechanical integration.

Specializations

Chip Architecture & Design — ASIC and accelerator design for training and inference workloads. Datapath architecture, memory hierarchy, on-chip interconnects, and the microarchitectural decisions that determine performance, power, and area tradeoffs.

Systems Hardware — Board design, server design, interconnects (NVLink, PCIe, CXL), cooling solutions, and power delivery. The physical integration layer between chips and data center infrastructure.

Hardware-Software Co-Design — ISA design, memory hierarchy optimization, compiler-hardware interface, and the joint decisions that make hardware programmable and efficient for ML workloads. Works closely with Compilers & Frameworks.

Fabrication, Packaging & Reliability — Takes chip designs from tape-out through fabrication, packaging, testing, and into volume production. Owns foundry interface, process node decisions, yield optimization, advanced packaging (CoWoS, chiplets), reliability qualification, failure analysis, and the manufacturing-design feedback loop.

Where the Work Lives

[1]Substrate

Primary

Designs custom silicon, manages fabrication, and owns the manufacturing pipeline from tape-out to production.

[2]Compute

Primary

Chip architecture decisions — datapath, memory hierarchy, interconnects — define AI compute capability.

[3]Intelligence

[4]Systems

[5]Distribution

Candidate Archetypes

Jim Harris

NVIDIA

Chip architect

Picks datapaths, memory hierarchies, interconnect assumptions, and programmability constraints that set the ceiling for training and inference efficiency.